1. Field of the Invention
The present invention relates to electronic circuits and systems. More specifically, the present invention relates to power dissipation in electronic circuits and systems.
2. Description of the Related Art
Power dissipation of electronic circuitry is an important design consideration for many applications. Power dissipation provides a measure of the efficiency of the system. The efficiency of the system impacts the design of the power supply for the system. That is, low efficiency leads to higher costs due to the waste of energy and the need for larger power supplies.
For battery powered systems, power dissipation limits battery life. This necessitates larger batteries which increases the cost and weight of the system while limiting the applicability thereof. As an example, consider coronary pacemakers where power dissipation is a critical concern due to the difficultly of accessing the battery for replacement and the cost and inconvenience associated with the use of larger batteries.
In addition, the dissipated energy is released in the form of heat. Accordingly, systems which exhibit considerable power dissipation often require measures such as heat sinks to protect or cool system components from the heat created by the circuit. The use of heat sinks and the like adds to the cost, size and weight of the system and thereby limits the utility of same.
For the CMOS (complementary-metal-oxide semiconductor) based system, used widely in the design of computers, digital logic circuits and the like, capacitive effects are primarily responsible for the dissipation of power. Such capacitive effects arise due to junction capacitances within semiconductor devices, interlead capacitances between lines connecting the circuit to external devices and the capacitance of a load.
In accordance with conventional teachings, power dissipation is directly related to the operating frequency (f), the capacitance (C) and the square of the voltage (V2) applied to the capacitive element.
In addition to the elimination of unnecessary capacitances and the reduction of the switching frequency to the lowest value that supports the functional specification of the circuit, most prior approaches to the problem have focused on reducing the voltage applied to the capacitive elements. However, in addition to costly interfacing issues, attempts to lower the voltage of digital processors and the like have been limited by the fact that the trend is to higher processing speeds which cannot be attained at arbitrarily low operating voltages.
Thus, there is an ongoing need in the art for a system and technique for minimizing the power dissipated by a digital system.
The need in the art is addressed by the present invention which, in a most general sense, provides a system and method for efficiently charging and discharging a capacitive load from a single voltage source. The inventive system includes a first switch for selectively connecting the voltage source to the load and a second switch for selectively providing a short across the load as may be common in the art. A particularly novel aspect of the invention resides in the provision of plural capacitive elements and a switching mechanism for selectively connecting each of the capacitive elements to the load whereby the load is gradually charged or discharged.
In the illustrative embodiment, the switching mechanism includes a set of switches for selectively connecting each of the capacitive elements to the capacitive load and a switch control mechanism for selectively activating the switches.